This invention relates to a semiconductor memory device and more particularly to a technique which will be particularly useful when utilized for a dynamic RAM (Random Access Memory) employing a split array system, for example.
Those dynamic RAMs are available which use, as their basic structure, a memory array including a plurality of word lines and complementary data lines disposed to cross mutually and orthogonally and a plurality of dynamic memory cells disposed in matrix at the points of intersection of these word lines and complementary data lines. A so-called "split array system" which splits the memory array in an extension direction of the complementary data lines and selectively activates the arrays in accordance with address signals is also known as one of the means for improving the operation speed of such dynamic RAMs and for reducing their power consumption.
The dynamic RAM employing the split array system is disclosed, for example, in Japanese Patent Laid-Open No. 293589/1987.
In the conventional dynamic RAM employing such a split array system, a plurality of row address decoders, sense amplifiers, column switches, complementary common data lines, and the like, are disposed in such a manner as to correspond to the memory arrays after splitting, and a write/read circuit such as a main amplifier is disposed to correspond to each complementary common data line.
The number of splitting of memory array is set to an optimal number in consideration of the effect brought forth by the array splitting and the influences on the chip area due to the increase in the number of sense amplifiers and the like. The memory arrays after splitting are selectively activated in accordance with a predetermined address signal to reduce power consumption of the dynamic RAM. However, substantial efficiency of utilization of the complementary common data lines drops because the memory arrays are selectively activated.
On the other hand, the data that is inputted or outputted at one time has turned to a multi-bit with the increase in the capacity of the dynamic RAM and in this point, too, the advantage of the split array system described above is exhibited. If the split number of the memory array is determined by giving priority to the multi-bit structure, however, the optimal condition described above cannot be satisfied and the number of the arrays that are activated simultaneously increases.